Enhanced Filter Coprocessor
10
The enhanced filter coprocessor (EFCOP) peripheral module functions as a general-purpose,
fully programmable filter. It has optimized modes of operation to perform single-channel and
multichannel real and complex finite impulse response (FIR) filtering with and without adaptive
FIR filtering and decimation or single-channel and multichannel infinite impulse response (IIR)
filtering. EFCOP filter operations complete concurrently with DSP56300 core operations, with
minimal CPU intervention. For optimal performance, the EFCOP has one dedicated Filter
Multiplier Accumulator (FMAC) unit. Thus, for filtering, the combination Core/EFCOP offers
dual MAC capabilities. Its dedicated modes make the EFCOP a very flexible filter coprocessor
with operations optimized for cellular base station applications. The EFCOP architecture also
allows adaptive FIR filtering in which the filter coefficient update is performed using any
fixed-point standard or non-standard adaptive algorithms—for example, the well-known Least
Mean Square (LMS) algorithm, the Normalized LMS, and customized update algorithms. In a
transceiver base station, the EFCOP can perform complex matched filtering to maximize the
signal-to-noise ratio (SNR) within an equalizer. In a transcoder base station or a mobile switching
center, the EFCOP can perform all types of FIR and IIR filtering within a vocoder, as well as
LMS-type echo cancellation. This chapter describes the EFCOP features, architecture, operation,
and programming model.
10.1 Features
Fully programmable real/complex filter machine with 24-bit resolution
FIR filter options
— Four modes of operation with optimized performance:
? Mode 0, FIR machine with real taps
? Mode 1, FIR machine with complex taps
? Mode 2, Complex FIR machine generating pure real/imaginary outputs alternately
? Mode 3—Magnitude (calculate the square of each input sample)
— 4-bit decimation factor in FIR filters providing up to 1:16 decimation ratio
— Easy to use adaptive mode supporting true or delayed LMS-type algorithms
— K-constant input register for coefficient updates (in adaptive mode)
IIR filter options:
— Direct form 1 (DFI) and direct form 2 (DFII) configurations
— Three optional output scaling factors (1, 8, or 16)
DSP56311 Reference Manual, Rev. 2
Freescale Semiconductor
10-1
相关PDF资料
DSPAUDIOEVMMB1E BOARD MOTHER DSP563XX
DSPIC30F2010 DEVELOPMENT KIT KIT DEV EMBEDDED C
DSTRM-KT-0181A DSTREAM DEBUG AND TRACE UNIT
DSUT1CSU SURGE SUPPR NETWORK W/GROUND
DTEL2 SURGE SUPPRESSOR PHONE RJ11/RJ45
DV003001 PROGRAMMER PICSTART PLUS 16C/17C
DV164035 MPLAB ICD3 IN-CIRC DEBUGGER
DV164039 KIT DEV PIC24FJ256DA210
相关代理商/技术参数
DSP56311EVMIG_D 制造商:未知厂家 制造商全称:未知厂家 功能描述:DSP56311EVMIG DSP56311EVM Sample Code
DSP56311EVMUM 制造商:未知厂家 制造商全称:未知厂家 功能描述:DSP56311 Evaluation Module Hardware Reference Manual
DSP56311FACT 制造商:未知厂家 制造商全称:未知厂家 功能描述:DSP56311 Higher performance programmable DSP for demanding voice and data applications
DSP56311UM 制造商:未知厂家 制造商全称:未知厂家 功能描述:DSP56311 24-Bit Digital Signal Processor Users Manual
DSP56311UMAD 制造商:未知厂家 制造商全称:未知厂家 功能描述:DSP56311 Users Manual Addendum
DSP56311VF150 功能描述:数字信号处理器和控制器 - DSP, DSC 150Mhz/300MMACS 150Mhz EFCOP RoHS:否 制造商:Microchip Technology 核心:dsPIC 数据总线宽度:16 bit 程序存储器大小:16 KB 数据 RAM 大小:2 KB 最大时钟频率:40 MHz 可编程输入/输出端数量:35 定时器数量:3 设备每秒兆指令数:50 MIPs 工作电源电压:3.3 V 最大工作温度:+ 85 C 封装 / 箱体:TQFP-44 安装风格:SMD/SMT
DSP56311VF150B1 功能描述:数字信号处理器和控制器 - DSP, DSC 24 BIT DSP RoHS:否 制造商:Microchip Technology 核心:dsPIC 数据总线宽度:16 bit 程序存储器大小:16 KB 数据 RAM 大小:2 KB 最大时钟频率:40 MHz 可编程输入/输出端数量:35 定时器数量:3 设备每秒兆指令数:50 MIPs 工作电源电压:3.3 V 最大工作温度:+ 85 C 封装 / 箱体:TQFP-44 安装风格:SMD/SMT
DSP56311VF150R2 功能描述:数字信号处理器和控制器 - DSP, DSC 24 BIT DSP RoHS:否 制造商:Microchip Technology 核心:dsPIC 数据总线宽度:16 bit 程序存储器大小:16 KB 数据 RAM 大小:2 KB 最大时钟频率:40 MHz 可编程输入/输出端数量:35 定时器数量:3 设备每秒兆指令数:50 MIPs 工作电源电压:3.3 V 最大工作温度:+ 85 C 封装 / 箱体:TQFP-44 安装风格:SMD/SMT